The present invention relates to a technology for manufacturing a semiconductor integrated circuit device and, more particularly, to a process for manufacturing a semiconductor integrated circuit device and a production control technology in a wafer process and a fabrication step.
The process for fabricating a semiconductor integrated circuit device is broadly divided into the following three steps, for example. That is to say: a wafer process; a wafer testing step and a fabrication step. The wafer process is one for forming an integrated circuit in a semiconductor wafer (which will be shortly referred to as the "wafer"). The wafer process is composed of a plurality of treating steps such as thin film forming step, a pattern transfer step, an etching step, an impurity doping step, a heat treating step and a rising step. The integrated circuit is formed in each of semiconductor chips (which will be shortly referred to as the "chips") over the wafer by combining those treating steps skillfully.
Incidentally, the production control at the unit of wafer has been performed in the wafer process of the prior art. According to the prior art, for example, tests for detecting a foreign substance or a pattern defect is performed in the wafer process, and the detected data are those for deciding the propriety of the wafer at the testing step. Specifically, the wafer, in which a predetermined number or more of chips are defective as a result of the tests, is disposed of. On the other hand, the wafer which has been tested to be free of defects is further processed.
After the end of all the treating steps of the wafer process, the wafer testing step is started. In the wafer testing step, the tip of a probe is brought into abutment against the electrodes of all the chips over the wafer to decide the propriety of each chip. It is not before this stage that the number of the non-defective or defective chips to be obtained from the wafer is clarified.
Incidentally, the wafer process technology is disposed on pp. 35 to 40 of "Recent Semiconductor Process Technology of '90" issued on Nov. 2, 1989 by PRESS JOURNAL, for example.
On the other hand, the testing technology of testing defects in the semiconductor wafer is disclosed in Japanese Patent Laid-Open No. 171736/1985 laid open on Sep. 5, 1985, for example.
On the other hand, the automation of VLSI manufacture is disclosed on pp. 736 to 739 of Technical Digest of 1988 IEEE IEDM (i.e., International Electron Devices Meeting) issued in 1988, for example,
Incidentally, we have found the following problems in the production control method in the aforementioned wafer process of the prior art.
Specifically, the prior art is troubled by a problem that the production control at the unit of chip is not performed in the wafer process, namely, that what is performed is the production control at the unit of wafer. As a result, the non-defective chips to be finally formed over the wafer which later becomes defective during further treatments raise shortage problems and any surplus chips resulting from deliberate excess wafer introduced to account for defective chips increase manufacturing costs and time.
In the prior art, for example, there are introduced into the wafer process excess wafers so that more chips than the desired final number of chips to account for the defective chips. Since the production control is not performed at the unit of chip in the prior art, the number of non-defective chips is unknown in the wafer process. As a result, all the chips over the wafer are treated notwithstanding whether or not the chips might be excessive. In case excessive chips are formed, there arises a problem that the number of treatments, materials and the time period for the treatments are wasted to an extent corresponding to the excessiveness.
In the prior art, on the other hand, the tests are performed in the wafer process, but no production control is performed at the unit of chip. Thus the propriety of each of the chips over the wafer is unknown. Therefore, all the chips over the wafer are treated notwithstanding their proprieties. In other words, even the chip, which has been deteriorated in the wafer process, is treated. This raises a problem that the number of treatments, materials and the time period for the treatments are wasted to an extent corresponding to the treatment of the defective chips. Especially in case the number of non-defective chips is short of the number of chips to be attained, the number of defective chips is large and wasteful. In case, moreover, the number of chips to be attained is short in the testing steps, new wafers have to be loaded to recover the shortage. In case the chips are short, there arises another problem that the production cost rises. In the prior art, still moreover, the number of short chips is not found till the end of the wafer testing step. Therefore, the start of manufacturing the short chips has to be delayed till the end of the wafer testing step. In case of short chips, therefore, there arises another problem that it takes a long time to retain a necessary number of non-defective chips, thus making it difficult to retain the delivery.
These problems are anticipated to become serious for the future trends in the semiconductor integrated circuit device, such as 1 customization, 2 high integration or enlargement, and 3 shortening of the time period for the delivery.
1 Customization: In recent years, it has been progressed to develop and manufacture customized products such as ASIC (i.e., Application Specific IC). In the customized products such as the ASIC, the chips designed according to the required specifications of a user are produced in a number required by the user. As a result, the kinds of products are usually increased, but the number of each product is smaller than that of memories or the like. As a result, a reduction in the production cost cannot be expected by the effect of mass production. Specifically, the production cost depends upon how a desired number of product chips is produced neither excessively nor shortly. In the production control method of the prior art, however, the fluctuations in the chip production yield are intense, and the obtainable non-defective chips are liable to become excessive or short, so that the production cost seriously fluctuates. As a result, it is difficult for the production control method of the prior art to cope with the productions of more kinds and less number.
2 High Integration and Enlargement: The semiconductor integrated circuit device has a coming trend to progress a larger capacity and a higher function. It is also apparent to progress the high integration of the elements and the enlargement of the chips. If the chips are enlarged, the number of chips to be formed over the wafer is reduced. Moreover, if the chips are large-sized and if the elements are highly integrated (to have a finer structure), the percentage of defects due to foreign substances is increased to drop the chip production yield. In the production control method of the prior art, the loss of the production cost is increased to raise the production cost. As a result, the production control method of the prior art finds it difficult to cope with the manufacture of a semiconductor integrated circuit device which is highly integrated to have larger chips.
3 Shortened Time Period for Delivery: The customized product such as the ASIC takes the more number and longer time period for its development as it is given the higher functions. On the contrary, the existing products go fast out of fashion to have shorter lifetimes. As a result, the requirements for shortening the time period from the development to the trial manufacture and for the delivery by the user get more and more strict. In the production control method of the prior art, however, the manufacture of the short chips cannot be started before the end of the wafer testing step. It takes a long time to retain a required number of chips. This discussion likely applies to the corrections or defect analyses of the mask at the trial stage. Thus, the production control method of the prior art finds it difficult to cope with the shortening the time period for delivery.